[1] 学術論文

(1) T. Tsuchiya, T. Yoshida, and Y. Sato, “Impact of Hot Carrier Stress on Low-Frequency Noise Characteristics in Floating-Body SOI MOSFETs”, Jpn J. Appl. Phys., vol. 41, Part 1, no. 7A, pp. 4427-4431, July 2002.

(2) T. Yamashiro, T. Kikuchi, M. Ishii, F. Honma, M. Sakuraba, T. Matsuura, J. Murota, and T. Tsuchiya, “Super Self-Aligned Technology of Ultra-Shallow Junction in MOSFETs Using Selective Si1-xGex CVD”, Materials Science & Engineering B, vol. 89/1-3, pp. 120-124, 2002.

(3) T. Tsuchiya, T. Matsuura, and J. Murota, “Low Frequency Noise in Si1-xGex p-Channel Metal-Oxide-Semiconductor Field-Effect-Transistors”, Jpn. J. Appl. Physc, vol. 40, Part 1, no. 9A, pp. 5290-5293, 2001.

(4) Y. Ishiakawa, M. Kosugi, T. Tsuchiya, and M. Tabe, "Concentration of Electric Field near Si Dot/Thermally-Grown SiO2 Interface", Jpn J. Appl. Phys., vol. 40, Part 1, no. 3B, pp. 1866-1869, 2001.

(5) 土屋, “SOI CMOSデバイス”, 信頼性,日本信頼性学会,vol. 23, no. 2, pp. 229-241, 2001年3月.

(6) T. Tsuchiya, “Recent Progress and Future Prospects of SOI CMOS”, Electronics and Communications in Japan, Part 2, vol. 83, no. 10, pp.24-34, 2000.

(7) Y. Sato and T. Tsuchiya, “Suppression of Floating Body Effects by Controlling Potential Profile in the Lower Body Region of Silicon-on-Insulator Metal-Oide-Semiconductor Field Effect Transistors", Jpn J. Appl. Phys., vol. 39, Part 1, no. 6A, pp. 3271-3276, June 2000.

(8) Y. Ishikawa, M. Kosugi, M. Kumezawa, T. Tsuchiya, and M. Tabe, Capacitance-voltage study of single-crystalline Si dots on ultrathin buried SiO2 formed by nanometer-scale local oxidation, Thin Solid Films, vol. 369, no. 1-2, pp. 69-72, 2000.
(9) T. Tsuchiya, K. Goto, M. Sakuraba, T. Matsuura, and J. Murota, Drain Leakage Current and Instability of Drain Current in Si/Si1-xGex MOSFETs, Thin Solid Films, vol. 369, no. 1-2, pp. 379-382, 2000.

(10) Y. Ishikawa, S. Makita, J. Zhang, M. Tabe, and T. Tsuchiya, “Capacitance-voltage study of silicon-on-insulator structure with an ultrathin buried SiO2 layer fabricated by wafer bonding”, Jpn. J. Appl. Phys., vol. 38, Part 2, no. 7B, pp. L789-L791, 15 July 1999.

(11) 土屋,SOI CMOSの現状と展望,電子情報通信学会論文誌C-I,vol. J82-C-I, no. 4, pp. 165-174, 1999年4月.

(12) Y. Sato, T. Kosugi, T. Tsuchiya, and H. Ishii, Improving the Characteristics of Ultra-Thin-Film Fully-Depleted Metal-Oxide-Semiconductor Field Effect Transistors on SIMOX (Separation by Implanted Oxygen) by Selective Tungsten Deposition on Source and Drain Region, Jpn. J. Appl. Phys., Part I, vol 37, no. 12A, pp. 6290-6294, Dec. 1998.

(13) Y. Sato, Y. Kado, T. Tsuchiya, T. Kosugi, and H. Ishii, 300 K-Gate Sea-of-Gate Type Gate Arrays Fabricated Using 0.25-μm-Gate Ultra-Thin-Film Fully-Depleted Complementary Metal-Oxide-Semiconductor Separation by Implanted Oxygen (CMOS/SIMOX) Technology with Tungsten-Covered Source and Drain, Jpn. J. Appl. Phys., Part I, vol 37, no. 11, pp. 5875-5879, Nov. 1998.

(14) T. Tsuchiya, Y. Sato, and M. Tomizawa, Three Mechanisms Determining Short Channel Effects in Fully-Depleted SOI MOSFETs, IEEE Trans. Electron Devices, vol. 45, no. 5, pp. 1116-1121, May 1998.

(15) T. Ohno, M. Takahashi, Y. Kado, and T. Tsuchiya, Suppression of Parasitic Bipolar Action in Ultra-Thin-Film Fully-Depleted nMOSFETs/SIMOX by Ar-Ion Implantation into Source/Drain Regions, IEEE Trans. Electron Devices, vol. 45, no. 5, pp. 1071-1076, May 1998.

(16) H. Koizumi, M. Shimaya, and T. Tsuchiya, Suppressing the Parasitic Bipolar Action in Fully-Depleted MOSFETs/SIMOX by Using Back-Side Bias-Temperature Treatment, IEEE Trans. Electron Devices, vol. 45, no. 4, pp. 933-938, April 1998.

(17) M. Harada, C. Yamaguchi, and T. Tsuchiya,
Investigation of a Multigigahertz MOSFET Amplifier with an On-Chip Inductor Fabricated on a SIMOX Wafer, IEEE Trans. Electron Devices, vol. 45, no. 1, pp. 173-178, 1998.


[2] 国際会議

(1) T. Tsuchiya, Y. Imada, and J. Murota, “Evaluation of Interface Trap Density in a SiGe/Si Heterostructure Using a Charge Pumping Technique and Correlation between the Trap Density and Low Frequency Noise in SiGe-Channel pMOSFETs,” 32th European Solid-State Device Research Conference, Firenze, Italy, pp. 239-242, Sep. 24-26, 2002.

(2) D. Lee, M. Sakuraba, J. Murota, and T. Tsuchiya, ”0.1-μm pMOSFETs with SiGe-Channel and B-Doped SiGe Source /Drain Layers,” International Conf. on Solid State Devices and Materials, Extended Abstract, Nagoya, pp. 764-765, Sep. 17-19, 2002.

(3) T. Yoshida, Y. Ebiko, M. Takei, N. Sasaki, and T. Tsuchiya, “Grain-Boundary Related Hot Carrier Degradation Mechanism in Low-Temperature Poly-Si Thin-Film-Transistors,” International Conf. on Solid State Devices and Materials, Extended Abstract, Nagoya, pp. 804-805, Sep. 17-19, 2002.

(4) H. Shim, M. Sakuraba, T. Tsuchiya, and J. Murota, “Electrical Properties of Impurity-Doped Polycrystalline Si1-x-yGexCy Films Using Ultraclean Low-Pressure CVD”, Int’l Conf. on Solid Films and Surfaces, Marseille, France, July 8-12, 2002.

(5) D. Lee, M. Sakuraba, T. Matsuura, J. Murota, and T. Tsuchiya, ”SiGe-Channel 0.1-μm pMOSFETs with Super Self-Aligned Ultra-Shallow Junction Formed by Selective In-Site B-Doped SiGe CVD”, 60th Annual Device Research Conference, Santa Barbara, June 24-26, 2002.

(6) Doohwan Lee, Masao Sakuraba, Junichi Murota, and Toshiaki Tsuchiya, “Fabrication of 0.1mm SiGe-Channel pMOSFETs with In-Situ B-Doped SiGe Source/Drain,” Second Int’l Workshop on New Group IV (Si-Ge-C) Semiconductors, VIII-05, Kofu, June 2-4, 2002.

(7) Hyunyoung Shim, Masao Sakuraba, Toshiaki Tsuchiya, and Junichi Murota, Work Function of Impurity-Doped Poly-Si1-x-yGexCy Film Deposited by Ultraclean Low-Pressure CVD,” Second Int’l Workshop on New Group IV (Si-Ge-C) Semiconductors, IV-10, Kofu, June 2-4, 2002.

(8) T. Tsuchiya, Y. Imada, and J. Murota, “Evaluation of SiGe/Si heterostructure interface-traps in SiGe-channel MOSFETs”, Second Int’l Workshop on New Group IV (Si-Ge-C) Semiconductors, VII-01, Kofu, June 2-4, 2002.

(9) T. Tsuchiya, Y. Imada, and J. Murota, “Exploration of SiGe/Si Heterostructure Interface in SiGe-Channel MOSFETs”, The Sixth Int’l Conference on Solid-State and Integrated-Circuit Technology, Shanghai, pp. 575-579, Oct. 22-25, 2001.(Invited paper)

(10) T. Tsuchiya, T. Yoshida, and Y. Sato, ”Impact of Hot Carrier Stress on Low-Frequency Noise Characteristics in Floating-Body SOI MOSFETs”, Int’l Conference on Solid State Devices and Materials, Tokyo, pp. 272-273, Sep. 26-28, 2001.

(11) T. Yamashiro, M. Sakuraba, T. Matsuura, J. Murota, and T. Tsuchiya, “Super Selef-Aligned Technology of Ultra-Shallow Junction in MOSFETs Using Selective Si1-xGex CVD”, The 2nd Int’l Conf. on Silicon Epitaxy and Heterostructures, Symp. D of the E-MRS 2001 Spring Meeting, June 4-8, 2001.

(12) Y. Ishikawa, T. Ishihara, T. Tsuchiya, and M. Tabe,”XPS and I-V Studies on Quantum Mechanical Effects in Ulytathin Si Layer of SOI Structure”, IEEE 2001 Silicon Nanoelectronics Workshop, Kyoto, June 10-11, 2001.

(13) T. Tsuchiya, T. Matsuura, and J. Murota,Low Frequency Noise in Si1-xGex-Channel pMOSFETs, Proc. of the 199th ECS Symp. on ULSI Process Integration II, Washington DC, pp. 205-210, March 26-29, 2001.

(14) T. Yamashiro, M. Sakuraba, T. Matsuura, J. Murota, and T. Tsuchiya, Fabrication of 0.1 μm MOSFETs with Super Self-Aligned Ultra-Shallow Junction Formed by Selective Si1-xGex CVD, Intl Workshop on New Group IV (Si-Ge-C) Semiconductors, II-07, Sendai, Strasbourg, France Jan. 21-23, 2001.

(15) T. Tsuchiya, T. Matsuura, and J. Murota, “Low-frequency-noise and its correlation with transconductance in Si1-xGex-channel pMOSFETs”, Int’l Workshop on New Group IV (Si-Ge-C) Semiconductors, II-01, Sendai, Jan. 21-23, 2001.

(16) Y. Ishikawa, M. Kosugi, T. Tsuchiya, and M. Tabe, ”Enhancement of Local Electric Field at Si Dot/Thermally-Grown SiO2 Interface”, to be presented at Int’l Symp. on Formation, Physics and Device Application of Quantum Dot Structures, Sep. 10-14, 2000.

(17) Y. Ishikawa, M. Kosugi, T. Tsuchiya, and M. Tabe, Fowler-Nordheim Tunneling Induced by Enhanced Local Electric Field in Si Dot Structure, Silicon Nanoelectronic Workshop, pp. 69-70, June 11-12, 2000.

(18) M. Yoshimi, S. Maegawa, T. Tsuchiya, M. Morita, K. Demizu, and T. Ohmi, "Evaluation of SOI Wafer Quality and Technological Issues to be Solved", Int'l Conf. on Solid State Devices and Materials, pp. 352-353, Sep. 1999 (Tokyo).

(19) Y. Ishikawa, M. Kosugi, M. Kumezawa, T. Tsuchiya, and M. Tabe, "C-V Study of Single-Crystalline Si Dots on Ultrathin Buried SiO2 Formed by Nano-LOCOS Process", Int'l Joint Conf. on Silicon Epitaxy and Heterostructures, B-8, Sep. 1999 (Miyagi, Zao).

(20) T. Tsuchiya, K. Goto, M. Sakuraba, T. Matsuura, and J. Murota, "Drain Leakage Current and Instability of Drain Current in Si/Si1-xGex MOSFETs", Int'l Joint Conf. on Silicon Epitaxy and Heterostructures, PII-14, Sep. 1999 (Miyagi, Zao).

(21) Y. Sato and T. Tsuchiya,
Suppression of floating body effects by controlling potential profile in the lower body region of SOI MOSFETs, SPIE Conf. on Microelectronic Device Technology, vol. 3881, pp. 62-72, Sep, 1999 (Santa Clara).

(21) Y. Ishikawa, S. Makita, J. Zhang, T. Tsuchiya, and M. Tabe,
Effects of Electron Tunneling into a Single-Crystalline Si Layer through an Ultrathin Buried Oxide, International Conf. on Solid State Devices and Materials, Extended Abstract, pp. 182-183, 1998.


[3] 研究会、委員会等

(1) 吉田俊幸,蛯子芳樹,竹井美智子,佐々木伸夫,土屋敏章,“結晶粒界が関与したpoly-Si TFTホットキャリア劣化機構”,応用物理学会中国四国支部研究会「SOIおよびTFTデバイス技術の現状と将来展望」,pp. 91-95,2002年11月21日-22日.

(2) 土屋敏章,今田祐二,室田淳一,”SiGe/SiヘテロMOSFETの雑音特性と界面準位”,電気学会 超高速SiGeデバイス材料調査専門委員会,2002年11月19日.

(3) 土屋敏章,“フローティング・ボディSOI MOSFETの低周波雑音特性におけるホットキャリア効果”,東北大学電気通信研究所共同プロジェクト研究「超高速・高精度気体絶縁金属基板SOIデバイス・プロセスの研究」研究会,2002年3月13日.

(4) 土屋,“SOIデバイスとの対話とこれから”,応用物理学会中国四国支部研究会,pp. 12-25,2001年11月16日.

(5) 土屋,SOIとSiGeデバイス −超高速Siデバイス−”,日本学術振興会,ナノプローブテクノロジー第167委員会第22回研究会資料,pp. 56-68,2001年7月13日.

(6) 石原,岩崎,土屋,石川,田部,“シリコン量子井戸構造の作製と評価”,電子情報通信学会,シリコン材料・デバイス研究会資料,SDM2001-43(2001-05),pp. 81-85,2001年5月25日.

(7) 土屋,松浦,室田,Si1-xGexチャネルpMOSFETにおける低周波雑音とSi1-xGex/Siヘテロ構造品質との対応,電子情報通信学会 シリコン材料・デバイス研究会資料SDM2001-41(2001-05),pp. 69-73,2001年5月25日.

(8) 吉見,前川,土屋,森田,出水,大見,“SOI基板材料の品質評価と技術課題”,電子情報通信学会,シリコン材料・デバイス研究会資料,SDM99-229,pp. 29-36,2000.3.

(9) 吉見,前川,土屋,森田,出水,大見,SOI基板の品質評価と今後の技術課題,日本学術振興会,超集積化デバイス・システム第165委員会 第13回研究会資料,pp. 1-8,2000.

(10) 土屋,室田,SOIデバイスのスケーリングと高性能化−SiGeの導入−,日本学術振興会,超集積化デバイス・システム第165委員会 第13回研究会資料,pp. 15-21,2000.

(11) 小泉,嶋屋,土屋,“バイアス・温度 (BT) 処理を用いたnMOSFET/SIMOXの特性改善”,電子情報通信学会,シリコンデバイス材料研究会資料,SDM99-219,pp. 61-67,1999.

(12) 土屋,SOI CMOSの現状と展望,電子情報通信学会,シリコン材料・デバイス研究会資料,SDM99-216,pp. 43-50,1999.

(13) 佐藤,小杉,門,土屋,大野,石井,西村,
選択W-CVDプロセスを導入した完全空乏型極薄膜CMOS/SIMOXゲートアレーLSI,電子情報通信学会,シリコン材料・デバイス研究会資料,SDM97-187,pp.7-14,1998.


[4] 学会講演会

(1) 北島毅顕,竹井美智子,佐々木伸夫,土屋敏章,“低温多結晶Si TFTにおける基板浮遊効果”,第4回IEEE HISS(IEEE広島支部学生シンポジウム),pp.81-81, 2002.12.5-6 (山口).

(2) 北島毅顕,竹井美智子,佐々木伸夫,土屋敏章,“低温多結晶Si TFTにおける閾値電圧のドレイン電圧依存性”,電気・情報関連学会中国支部 第53回連合大会,pp. 65-66,2002.10.19-20(島根大学).

(3) 土屋敏章,“MOSトランジスタの誕生・発展過程と薄膜電界効果トランジスタの挑戦”,電気・情報関連学会中国支部 第53回連合大会,特別講演,pp. 特1-2,2002.10.19-20(島根大学).

(4) 吉田俊幸,土屋敏章,蛯子芳樹,竹井美智子,佐々木伸夫“結晶粒界が関与した多結晶Si TFTのホットキャリア劣化モデルの検討”,第63回応用物理学会学術講演会,26p-G-13,2002.9.24-27(新潟大学).

(5) 吉田俊幸,土屋敏章,蛯子芳樹,三島康由,佐々木伸夫,“エキシマレーザ結晶化低温多結晶Si TFTのホットキャリア劣化機構”,第49回応用物理学関係連合講演会,30a-H-3,2002.3.27-30(東海大学).

(6) 吉田,土屋,“ポリシリコンTFTのホットキャリア劣化のストレスゲート電圧依存性”,第62回応用物理学会学術講演会,14a-P13-18,2001.9月(愛知工大).

(7) 今田,松浦,室田,土屋,“チャージポンピング法によるSiGeチャネルMOSFETのヘテロ界面評価”,第62回応用物理学会学術講演会,13a-P9-11,2001.9月(愛知工大).

(8) 今田,室田,土屋,“SiGeチャネルpMOSFETにおけるSiGe/Siヘテロ界面準位の評価”,応用物理学会中国四国支部2001年度支部例会,Ea-9,2001.8月(鳥取大).

(9) 土屋,桜庭,松浦,室田,SOI MOSFETおよびSiGeチャネルMOSFETの低周波雑音特性,第61回応用物理学会学術講演会,6p-ZE-6, 2000.

(10) 土屋,櫻庭,松浦,室田,”Si/Si1-xGex MOSFETにおけるドレインリーク電流の解析”,第60回応用物理学会学術講演会,2p-ZL-10,1999.

(11) 土屋,佐藤,SOI MOSFETにおける下部ボディ領域の電位分布制御による基板浮遊効果の抑制,第46回応用物理関係連合講演会,30p-ZM-4,1999.

(12) 牧田,石川,張,土屋,田部,極薄埋め込みSiO2層を持つSOI構造のC-V特性,第59回応用物理学会学術講演会,16a-YG-1,1998.

(13) 土屋,佐藤,富沢,
極薄膜SOI MOSFETにおけるソース・チャネル間寄生抵抗の検討,第45回応用物理関係連合講演会,30p-YB-7,1998.


[5] 学内報
(1) 土屋,
低消費電力・高速CMOS/SOIデバイス技術,島根大学総合理工学部紀要,シリーズA, vol. 32, pp. 111-129, 1998.



研究業績 (1998年−2002年)