研究業績(2003年)

[1] 学術論文
(1)  T. Yoshida, Y. Ebiko, M. Takei, N. Sasaki, and T. Tsuchiya, “Grain-Boundary Related Hot Carrier Degradation Mechanism in Low-Temperature Polycrystalline Silicon Thin-Film-Transistors,” Jpn. J. Appl. Phys., vol. 42, Part 1, no. 4B, pp. 1999-2003, April 2003.

(2) H. Shim, M. Sakuraba, T. Tsuchiya, and J. Murota, “Work function of impurity-doped polycrystalline Si1-xGexCy film deposited ultraclean low-pressure CVD”, Applied Surface Science 212-213, pp. 209-212, 2003.

(3) T. Tsuchiya, Y. Imada, and J. Murota, “Direct Measurements of Trap Density in a SiGe/Si Hetero-Interface and Correlation between the Trap Density and Low Frequency Noise in SiGe-Channel pMOSFETs”, IEEE Trans. Electron Devices, IEEE Trans. Electron Devices, vol. 50, no. 12, pp. 2507-2512, Dec. 2003.


[2] 国際会議
(1) T. Tsuchiya, Y. Imada, and J. Murota, “Low Frequency Noise and Hetero-Interface Traps in SiGe-Channel pMOSFETs,” First Int’l SiGe Technology and Device Meeting, Nagoya, Japan, pp. 33-34, Jan. 15-17, 2003.

(2) D. Lee, S. Takehiro, M. Sakuraba, J. Murota, and T. Tsuchiya, “Fabrication of 0.12-mm SiGe-Channel MOSFET Containing High Ge Fraction with Ultrashallow Source/Drain Formed by Selective B-Doped SiGe CVD,” First Int’l SiGe Technology and Device Meeting, Nagoya, Japan, pp. 17-18, Jan. 15-17, 2003.

(3) S. Takehiro, D. Lee, M. Sakuraba, J. Murota, and T. Tsuchiya, “Characterization of High Ge Fraction SiGe-Channel MOSFET with Ultrashallow Source/Drain Formed by Selective B-Doped SiGe CVD,” Third Int’l Conference on SiGe(C) Epitaxy and Heterostructures (ICSI3), Santa Fe, New Mexico, USA, pp. 179-181, March 9-12, 2003.

(4) T. Tsuchiya and J. Murota, “Noise properties and hetero-interface trap in SiGe-Channel pMOSFETs,” Proc. of the 203th Electrochemical Society Meeting, Symp. on ULSI Process Integration III, Paris, France, pp. 241-252, April 28-29, 2003. (Invited Paper)

(5) T. Yoshida, K. Yoshino, M. Takei, A. Hara, N. Sasaki, and T. Tsuchiya, “Experimental Evidence of Grain-Boundary Related Hot-Carrier Degradation Mechanism in Low-Temperature Poly-Si Thin Film-Transistors”, Tech. Digest of IEDM (Intn’l Electron Devices Meeting), Washington DC, pp. 219-222, Dec. 8-10, 2003.


[3] 研究会、委員会等
(1) 宝玉 充,土屋敏章,“部分空乏型SOI MOSFETにおけるダイオード電流の計算方法”,電子情報通信学会,シリコン材料・デバイス研究会,信学技報Vol. 103,No. 259,SDM2003-117,pp. 1-6,2003.8.21-22.

(2) 宝玉  充,土屋敏章,“Si-NMOSFETのキャリア熱速度の計算−チャネル不純物濃度,backscattering係数,並びにチャネルSi膜厚依存性−”,電子情報通信学会,シリコン材料・デバイス研究会資料,信学技報vol. 103,no. 533,SDM2003-184,pp. 31-38,2003.12.19.


[4] 学会講演会
(1) 土屋敏章,今田祐二,室田淳一,“SiGeチャネルpMOSFETの低周波雑音特性とヘテロ界面準位密度”,第50回応用物理学関係連合講演会 シンポジウム「W族半導体SiGe(C)ヘテロ構造素子の新展開」,28p-YE-8,2003.3.27-30 (神奈川大学).(招待講演)

(2) 室田淳一,櫻庭政夫,竹廣忍,土屋敏章,“SiGe系デバイスの微細化と原子制御プロセス”,第50回応用物理学関係連合講演会 シンポジウム「W族半導体SiGe(C)ヘテロ構造素子の新展開」,28p-YE-7,2003.3.27-30 (神奈川大学).(招待講演)

(3) 山村星史,吉野健一,竹井美智子,佐々木伸夫,土屋敏章,”低温多結晶シリコンTFTの低温特性“,応用物理学会中国四国支部 2003年度支部例会,EP-10,2003.8.2 (山口大学).

(4) 竹廣忍,櫻庭政夫,室田淳一,土屋敏章,”極浅ソース・ドレイン形成による極微細SiGeヘテロチャネルpMOSFETの高性能化“,第64回応用物理学会学術講演会 シンポジウム「最先端SiGe(C)技術とそのデバイス応用」,30p-ZD-5,2003.8.30-9.2(福岡大学).(招待講演)